module smg2(rst,clk_out2,d[7:0],dig[2:0],seg[7:0]);
input clk_out2,rst;
input [7:0] d;
output [2:0] dig;
output [7:0] seg;
reg [7:0] seg;
reg [7:0]seg1;
reg [7:0]seg2;
reg [2:0] dig;
always@(posedge clk_out2)
begin
if(!rst)
	dig<=3'd0;
	else
	if(dig==3'd1)
	dig<=3'd0;
	else 
	dig<=dig+1;
end
always @(dig)
begin
	case(dig)
		1:seg<=seg1; //秒个位
		0:seg<=seg2; //秒十位
	endcase
end

always@(d)
begin
case(d[3:0])
		0:seg1<=8'h3f;  
		1:seg1<=8'h06;
		2:seg1<=8'h5b;
		3:seg1<=8'h4f;
		4:seg1<=8'h66;
		5:seg1<=8'h6d;
		6:seg1<=8'h7d;
		7:seg1<=8'h07;
		8:seg1<=8'h7f;
		9:seg1<=8'h6f;
	endcase
end
always@(d)
begin
case(d[7:4])
		0:seg2<=8'h3f; 
		1:seg2<=8'h06; 
		2:seg2<=8'h5b; 
		3:seg2<=8'h4f; 
		4:seg2<=8'h66; 
		5:seg2<=8'h6d; 
	endcase
end
endmodule
